Google trains chips to design themselves

Qubit Mechanical Resonator
(Credits - Wikimedia Commons)

Google always attracts us with its ingenious inventions. They bring us one more interesting invention. Read this article to discover out more.

Google has now trained chips that design itself. One key challenge in designing computers is the packing of chips and wiring in the most ergonomic fashion, maintaining power, speed, and energy efficiency.

On a piece of real estate the size of a fingernail that thousands of components must communicate with one another flawlessly to make this possible.

Chip floor planning is the name of the process. It is like what interior decorators do when laying out plans to dress up a room. Designers must consider integrated layouts within multiple floors in case of Digital circuitry unlike using a one-floor plan.

The shortcoming of the process is that it is time-consuming. And with continual improvement in chip components, laboriously calculated final designs become outdated fast. We design chips in such a way that their life span goes between two and five years, but there is constant pressure to shorten the time between upgrades.

The breakthrough comes here. Senior Google research engineers Anna Goldie and Azalia Mirhoseini said they have designed an algorithm that “learns” how to achieve optimum circuitry placement. It can do so in a fraction of the time required for such designing, analyzing millions of possibilities instead of thousands, which is the norm. In doing so, it can provide chips that take advantage of the latest developments faster, cheaper and smaller.

Reinforcement learning was applied here. The system generates “rewards” and “punishments” for each proposed design until the algorithm better recognizes the best approaches.

Researchers at Google added that there was extensive testing that took place and it was that led to finding their fresh approach to artificially intelligent assembly line production. These designs were superior to the designs created by human engineers.

The designers said that it was their belief in AI that AI will provide them the solution to shorten the chip design cycle and thus paving way for a relation between AI and hardware.

This new algorithm could also help ensure the continuation of Moore’s Law, which states the number of transistors packed into microchips doubles every one or two years. In 1970, Intel’s 4004 chip housed 2,250 transistors. Today, the AMD Epyc Rome hosts 39.5 billion transistors.

This invention thus leaves plenty of possibilities for Google’s new room design algorithm.

This was published in arxiv


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